This invention relates to data interface mechanisms for use in digital data processing systems for interfacing bit-parallel data buses of different bit width. While not limited thereto, this invention is particularly useful for coupling I/O units to a host processor wherein the I/O unit data bus is of a different bit width than the host processor channel data bus.
It has been heretofore proposed to connect a wider data bus to a narrower data bus by means of a data register having a width corresponding to that of the wider data bus. Selector circuitry is then used for connecting different portions of the data register to the narrower data bus one at a time in an appropriate sequence. While providing satisfactory operation in some applications, this kind of an interfacing mechanism can present a bottleneck to the movement of data in other applications. In particular, where multiple data handling units are connected to one side of the interface mechanism and the data handling units on opposite sides of the interface mechanism are not always ready to do a data transfer at the same moments, then delays can be encountered where one of the multiple units has to wait on the completion of a data transfer for another of the multiple units.
Take, for example, the case of an I/O controller which is used to couple multiple I/O devices to the I/O channel bus of a host processor, wherein the data buses which couple the I/O units to the I/O controller have a width of one byte and the I/O channel data bus has a multiple byte width. In this case, the host processor might transfer a multi-byte data word to an interface mechanism data register in the I/O controller for subsequent retransfer to a first I/O unit A. If the I/O unit A should not be ready to receive such data, then the data must remain in the data register. In such case, a second I/O unit B, which is ready to transfer data to the host processor, would have to sit and wait until the data register in the interface mechanism became available. Thus, for the case of multiple I/O units, the use of such a data register for interface purposes would represent a definite bottleneck in the system.
This bottleneck problem could be alleviated to some extent by providing separate data registers for each of the different I/O units. This, however, would increase the circuit complexity and would require further circuitry for determining which of the data registers should be connected to the I/O channel bus at any given moment. The bottleneck problem might also be alleviated to some extent by using some further form of storage mechanism for immediately removing the multi-byte data word from the interface mechanism data register after it is received from the host processor or, conversely, for not transferring any data from the I/O unit to the interface mechanism data register until a complete multi-byte word has been assembled. This, however, would require additional circuitry and would, in general, tend to increase the number of steps involved in the overall transfer of data from the host processor to an I/O unit, or vice versa.
There is described herein a new and improved data interface mechanism for interfacing bit-parallel data buses of different bit width in a more flexible and efficient manner, particularly where the interface mechanism is shared by multiple data handling units. In the embodiment illustrated herein, this improved data interface mechanism provides an automatic and highly efficient mechanism for converting data bytes into data words, and vice versa.
For a better understanding of the present invention, together with other and further advantages and features thereof, reference is made to the following description taken in connection with the accompanying drawings, the scope of the invention being pointed out in the appended claims.